`timescale 1ns/1ns    //时间单位:1ns, 时间精度:1ns

module water_led_tb;
    reg 		sys_clk;
    reg 		sys_rst_n;    
    wire [3:0] 	led;   

//------------<设置初始测试条件>----------------------------------------	 
	initial begin
		sys_clk     =    1'b1;
      	sys_rst_n   <=   1'b0; 
		#20
		sys_rst_n   <=   1'b1;
    end

//------------<设置时钟>----------------------------------------------	 
	 always #10 sys_clk = ~sys_clk;

//------------<例化被测试模块>----------------------------------------	
	water_led u_water_led
   (
	.sys_clk     (sys_clk)		,
	.sys_rst_n   (sys_rst_n)	,
	.led         (led)  
   );
   
   
	 
endmodule

